1. Field of the Invention
The present invention relates in general to a transconductance amplifier for suppling an output current which is proportional to a signal voltage, and more particularly, to a transconductance amplifier for embodying a constant voltage source that utilizes parasitic bipolar transistors which are present in the fabrication of CMOS devices so that the circuit can have a reduced number of components and improved electric characteristics.
2. Description of the Prior Art
With reference to FIG. 1, there is shown a circuit diagram of a basic construction of a conventional transconductance amplifier for explanation of the fundamental principles of the amplifier. The illustrated transconductance amplifier comprises an active load 1, and a pair of NMOS transistors NM1 and NM2 including their gate terminals connected respectively to positive/negative input signal terminals Vin.sup.+ and Vin.sup.-, their source terminals connected respectively to cathode terminals of bias voltage sources V.sub.B ' and V.sub.B, anode terminals of which are connected respectively between the negative input signal terminal Vin.sup.- and the gate of the NMOS transistor NM2 and between the positive input signal terminal Vin.sup.+ and the gate of the NMOS transistor NM1, and their drain terminals connected to the active load 1. Also, a current output terminal Iout is connected between the active load 1 and the drain terminal of the NMOS transistor NM2.
The operation of the conventional transconductance amplifier with the above-mentioned basic construction will now be described.
If the drain currents of the NMOS transistors NM1 and NM2 are designated respectively as I.sub.D1 and I.sub.D2, they can be expressed as follows: EQU I.sub.D1 =K1(V.sub.B +Vin/2-V.sub.T).sup.2 ( 1) EQU I.sub.D2 =K2(V.sub.B -Vin/w-V.sub.T).sup.2 ( 2)
where K1 and K2 are transconductance constants of the NMOS transistors NM1 and NM2 and V.sub.T is a threshold voltage.
Supposing that the NMOS transistors NM1 and NM2 are the same in size, the relationship between the transconductance constants thereof is established as K1=K2=K and thus the following equation (3) is obtained: EQU Iout=I.sub.D1 -I.sub.D2 =K(V.sub.D -V.sub.T)Vin (3)
where V.sub.D is a drain voltage of the NMOS transistors NM1 and NM2.
Therefore, a circuit meeting the above equation (3) can embody the basic construction of the transconductance amplifier.
With reference to FIG. 2, there is shown a circuit diagram of an embodiment of the conventional transconductance amplifier. In this drawing, the conventional transconductance amplifier comprises an active load 1, an amplifying section 2 and a bias section 3.
The amplifying section 2 is provided with a pair of NMOS transistors NM1 and NM2 including their gate terminals connected respectively to positive/negative input signal terminals Vin.sup.+ and Vin.sup.-, their drain terminals connected to the active load 1 and their source terminals connected respectively to bias supplying terminals of the bias section 3. Also, a current output terminal Iout is connected between the active load 1 and the drain terminal of the NMOS transistor NM2.
On the other hand, the bias section 3 is provided with a pair of NMOS transistors NM3 and NM4 including their gate terminals connected respectively to the positive/negative input signal terminals Vin.sup.+ and Vin.sup.-, their drain terminals connected to a voltage source terminal V.sub.DD and their source terminals connected respectively to the source terminals of the NMOS transistors NM2 and NM1 in the amplifying section 2. Also, current sources Is1 and Is2 are connected respectively between the the source terminal of the NMOS transistor NM3 and a ground terminal and between the source terminal of the NMOS transistor NM4 and the ground terminal.
With reference to FIG. 3, there is shown a circuit diagram of an alternative embodiment of the conventional transconductance amplifier. In this drawing, the conventional transconductance amplifier comprises an amplifying section 2', a bias section 3' and a current output section 4.
The amplifying section 2' is provided with a pair of NMOS transistors NM1 and NM2 including their gate terminals connected respectively to positive/negative input signal terminals Vin.sup.+ and Vin.sup.-, their source terminals connected respectively to bias supplying terminals of the bias section 3'.
Also, the bias section 3' is provided with a pair of NMOS transistors NM3 and NM4 including their gate terminals connected respectively to the positive/negative input signal terminals Vin.sup.+ and Vin.sup.-, PMOS transistors PM1, PM2, PM3 and PM4 including their source terminals connected to the voltage source terminal V.sub.DD, and NMOS transistor NM5, NM6, NM7 and NM8 including their source terminals connected to a ground terminal. Drain terminals of the NMOS transistors NM3 and NM4 are connected respectively to common gate terminals of the PMOS transistors PM1 and PM2 and common gate terminals of the PMOS transistors PM3 and PM4, and respectively to drain terminals of the PMOS transistors PM2 and PM3. Source terminals of the NMOS transistors NM3 and NM4 connected respectively to the source terminals of the NMOS transistors NM2 and NM1 in the amplifying section 2', and respectively to drain terminals of the NMOS transistors NM6 and NM7. Also, current sources Is1 and Is2 are connected respectively between the source terminal of the NMOS transistor NM3 and the ground terminal and between the source terminal of the NMOS transistor NM4 and the ground terminal. On the other hand, drain terminals of the PMOS transistors PM1 and PM4 are connected respectively to drain terminals of the NMOS transistors NM5 and NM8, and respectively to common gate terminals of the NMOS transistors NM5 and NM6 and common gate terminals of the NMOS transistors NM7 and NM8.
On the other hand, the current output section 4 is provided with a PMOS transistor PM5 including its gate terminal connected to the common gate terminals of the PMOS transistors PM3 and PM4 in the bias section 3' and its source terminal connected to the voltage source terminal V.sub.DD, and an NMOS transistor NM9 including its gate terminal connected to the common gate terminal of the NMOS transistors NM5 and NM6 in the bias section 3', its source terminal connected to the ground terminal and its drain terminal connected to drain terminal of the PMOS transistor PM5. Also, a current output terminal Iout is connected to the common drain terminal of the PMOS transistor PM5 and the NMOS transistor NM9.
The operation of the conventional transconductance amplifier with the above-mentioned construction with reference to FIG. 2 is substantially the same as that of the basic construction described with reference to FIG. 1, with the exception that the NMOS transistors NM3 and NM4 in the bias section 3 are large in size and the current from the current sources (Is1=Is2) are large in value, for the purpose of embodying the bias voltage sources V.sub.B and V.sub.B ' for applying the bias voltages respectively between the gate terminals of the NMOS transistors NM1 and NM2 and the source terminals of the NMOS transistors NM2 and NM1, as shown in FIG. 1.
On the other hand, in the alternative embodiment of the conventional transconductance amplifier described with reference to FIG. 3, feedback circuits of current mirror constructions are used to compensate the currents flowing between the drain terminals and the source terminals of the NMOS transistors NM3 and NM4 in the bias section 3'. Namely, the MOS transistors PM1, PM2, NM5 and NM6 and the MOS transistors PM3, PM4, NM7 and NM8 in the bias section 3' constitute respective current mirrors which are driven respectively by the NMOS transistors NM3 and NM4. As a result, the drain currents of the NMOS transistors NM3 and NM4 are fed back to the source terminals thereof, resulting in supplying the bias voltages respectively to the source terminals of the NMOS transistors NM2 and NM1 in the amplifying section 2'. Thus, the NMOS transistors NM3 and NM4 operate as constant voltage sources to the NMOS transistors NM2 and NM1. In the current output section 4, a mirror current difference is outputted through the current output terminal Iout which is based on the positive/negative input signals Vin.sup.+ and Vin.sup.- flowing through the bias section 3', due to the respective connections of the gates of the MOS transistors PM5 and NM9 with the common gates of the current mirror MOS transistors PM3, PM4, NM5 and NM6 in the bias section 3'.
However, the conventional transconductance amplifier has a disadvantage in that the chip is limited in size, since the NMOS transistors NM3 and NM4 in the bias section 3 must be large in size and the current from the current sources (Is1=Is2) must be large in value as described with reference to FIG. 2. Namely, the limitation in the size of the chip has a bad effect on the high integration of the chip. Also, the conventional transconductance amplifier has another disadvantage in that a multiplicity of devices are used to constitute the current mirror circuits, by which the bias voltages are supplied as the constant voltages, as described with reference to FIG. 3. That is, the use of the multiplicity of devices results in an increase in price and a degradation in precision, i.e., deterioration in electric characteristics and reduction in reliability.